Veryl language preview
1. Parameterized data selector
colon-typed ports and an always_ff/if_reset block
horizon-dark
pub module DataSelector #(
param Width: u32 = 8,
) (
i_clk : input clock ,
i_rst : input reset ,
i_sel : input logic ,
i_data: input logic<Width> [2],
o_data: output logic<Width> ,
) {
var r_data: logic<Width>;
always_ff {
if_reset {
r_data = 0;
} else if i_sel {
r_data = i_data[0];
} else {
r_data = i_data[1];
}
}
assign o_data = r_data;
} atom-one-dark
pub module DataSelector #(
param Width: u32 = 8,
) (
i_clk : input clock ,
i_rst : input reset ,
i_sel : input logic ,
i_data: input logic<Width> [2],
o_data: output logic<Width> ,
) {
var r_data: logic<Width>;
always_ff {
if_reset {
r_data = 0;
} else if i_sel {
r_data = i_data[0];
} else {
r_data = i_data[1];
}
}
assign o_data = r_data;
} github-dark
pub module DataSelector #(
param Width: u32 = 8,
) (
i_clk : input clock ,
i_rst : input reset ,
i_sel : input logic ,
i_data: input logic<Width> [2],
o_data: output logic<Width> ,
) {
var r_data: logic<Width>;
always_ff {
if_reset {
r_data = 0;
} else if i_sel {
r_data = i_data[0];
} else {
r_data = i_data[1];
}
}
assign o_data = r_data;
} dracula
pub module DataSelector #(
param Width: u32 = 8,
) (
i_clk : input clock ,
i_rst : input reset ,
i_sel : input logic ,
i_data: input logic<Width> [2],
o_data: output logic<Width> ,
) {
var r_data: logic<Width>;
always_ff {
if_reset {
r_data = 0;
} else if i_sel {
r_data = i_data[0];
} else {
r_data = i_data[1];
}
}
assign o_data = r_data;
} nord
pub module DataSelector #(
param Width: u32 = 8,
) (
i_clk : input clock ,
i_rst : input reset ,
i_sel : input logic ,
i_data: input logic<Width> [2],
o_data: output logic<Width> ,
) {
var r_data: logic<Width>;
always_ff {
if_reset {
r_data = 0;
} else if i_sel {
r_data = i_data[0];
} else {
r_data = i_data[1];
}
}
assign o_data = r_data;
} github
pub module DataSelector #(
param Width: u32 = 8,
) (
i_clk : input clock ,
i_rst : input reset ,
i_sel : input logic ,
i_data: input logic<Width> [2],
o_data: output logic<Width> ,
) {
var r_data: logic<Width>;
always_ff {
if_reset {
r_data = 0;
} else if i_sel {
r_data = i_data[0];
} else {
r_data = i_data[1];
}
}
assign o_data = r_data;
} 2. Interface with a modport
a shared bus interface restricted to a driving role
horizon-dark
interface DataBus #(param Width: u32 = 8) {
var data: logic<Width>;
var valid: logic;
modport master {
data: output,
valid: output,
}
} atom-one-dark
interface DataBus #(param Width: u32 = 8) {
var data: logic<Width>;
var valid: logic;
modport master {
data: output,
valid: output,
}
} github-dark
interface DataBus #(param Width: u32 = 8) {
var data: logic<Width>;
var valid: logic;
modport master {
data: output,
valid: output,
}
} dracula
interface DataBus #(param Width: u32 = 8) {
var data: logic<Width>;
var valid: logic;
modport master {
data: output,
valid: output,
}
} nord
interface DataBus #(param Width: u32 = 8) {
var data: logic<Width>;
var valid: logic;
modport master {
data: output,
valid: output,
}
} github
interface DataBus #(param Width: u32 = 8) {
var data: logic<Width>;
var valid: logic;
modport master {
data: output,
valid: output,
}
} 3. Generic function in a package
a width-parameterized adder using the ::<> generic call
horizon-dark
package Utilities {
function add::<W: u32>(
a: input logic<W>,
b: input logic<W>,
) -> logic<W> {
return a + b;
}
} atom-one-dark
package Utilities {
function add::<W: u32>(
a: input logic<W>,
b: input logic<W>,
) -> logic<W> {
return a + b;
}
} github-dark
package Utilities {
function add::<W: u32>(
a: input logic<W>,
b: input logic<W>,
) -> logic<W> {
return a + b;
}
} dracula
package Utilities {
function add::<W: u32>(
a: input logic<W>,
b: input logic<W>,
) -> logic<W> {
return a + b;
}
} nord
package Utilities {
function add::<W: u32>(
a: input logic<W>,
b: input logic<W>,
) -> logic<W> {
return a + b;
}
} github
package Utilities {
function add::<W: u32>(
a: input logic<W>,
b: input logic<W>,
) -> logic<W> {
return a + b;
}
}